* [MLIR] Enable affine loop tiling

This PR enables loop tiling optimization in affine dialect. It
introduces the following flags for configuration.
  - affine-loop-tile: enables/disables the optimization. Disabled by
    default.
  - loop-tile-cache-level: provides the cache level to which apply loop
    tiling to. Cache level size is obtained from LLVM's TTI.
  - loop-tile-cache-size: provides a cache level size that overrides
    cache information from TTI.

The current use of TTI is a bit hacky since we have to pass a fake
LLVM's function to make it work. However, this should be enough to get
some basic target information until we have a target model in MLIR or
find a better approach.

* Address feedback

* Rename flags