Core dump analysis improvements

 * ARM
   * Provide MSP and PSP
   * Provide FreeRTOS task info
   * Profide target specification XML (extra regs and FPU / no FPU Cortex cores)
 * ESP32
   * Use uxTaskGetSystemState instead of uxTaskGetTaskHandles
 * General cleanup and refactoring

CL: Core dump analysis improvements

PUBLISHED_FROM=3297ffb2e6069a3a6a598367273bc2183063cf1e

src/common/platforms/arm/arm_exc.c

@@ -15,6 +15,8 @@
  * limitations under the License.
  */
 
+#include "arm_exc.h"
+
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -31,32 +33,6 @@
 #define MGOS_ENABLE_CORE_DUMP 1
 #endif
 
-struct arm_exc_frame {
-  uint32_t r0;
-  uint32_t r1;
-  uint32_t r2;
-  uint32_t r3;
-  uint32_t r12;
-  uint32_t lr;
-  uint32_t pc;
-  uint32_t xpsr;
-#if __FPU_PRESENT
-  uint32_t s[16];
-  uint32_t fpscr;
-  uint32_t reserved;
-#endif
-} __attribute__((packed));
-
-struct arm_gdb_reg_file {
-  uint32_t r[13];
-  uint32_t sp;
-  uint32_t lr;
-  uint32_t pc;
-  uint32_t cpsr;
-  uint64_t d[16];
-  uint32_t fpscr;
-} __attribute__((packed));
-
 #if __FPU_PRESENT && !defined(MGOS_BOOT_BUILD)
 static void save_s16_s31(uint32_t *dst) {
   __asm volatile(
@@ -91,6 +67,12 @@ static void print_fpu_regs(const uint32_t *regs, int off, int n) {
 }
 #endif
 
+static struct arm_gdb_reg_file *s_rf = NULL;
+
+void arm_exc_dump_regs(void) {
+  mgos_cd_write_section(MGOS_CORE_DUMP_SECTION_REGS, s_rf, sizeof(*s_rf));
+}
+
 void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
                             struct arm_gdb_reg_file *rf) {
   char buf[8];
@@ -99,6 +81,7 @@ void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
   MPU->CTRL = 0;  // Disable MPU.
 #endif
   portDISABLE_INTERRUPTS();
+  s_rf = rf;
   switch (isr_no) {
     case 0:
       name = "ThreadMode";
@@ -157,10 +140,12 @@ void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
                    rf->r[8], rf->r[9], rf->r[10], rf->r[11]);
     mgos_cd_printf("  R12: 0x%08lx  SP:  0x%08lx   LR: 0x%08lx  PC:  0x%08lx\n",
                    rf->r[12], rf->sp, rf->lr, rf->pc);
-    mgos_cd_printf("  PSR: 0x%08lx\n", rf->cpsr);
+    mgos_cd_printf("  PSR: 0x%08lx MSP:  0x%08lx  PSP: 0x%08lx\n", rf->xpsr,
+                   rf->msp, rf->psp);
   }
+#if __FPU_PRESENT
   memset(rf->d, 0, sizeof(rf->d));
-#if __FPU_PRESENT && !defined(MGOS_BOOT_BUILD)
+#if !defined(MGOS_BOOT_BUILD)
   rf->fpscr = ef->fpscr;
   memcpy((uint8_t *) rf->d, ef->s, sizeof(ef->s));
   print_fpu_regs((uint32_t *) rf->d, 0, ARRAY_SIZE(ef->s));
@@ -173,11 +158,9 @@ void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
 #else
   rf->fpscr = 0;
 #endif
+#endif
 #if MGOS_ENABLE_CORE_DUMP
-  mgos_cd_emit_header();
-  mgos_cd_emit_section(MGOS_CORE_DUMP_SECTION_REGS, rf, sizeof(*rf));
-  mgos_cd_emit_section("SRAM", (void *) SRAM_BASE_ADDR, SRAM_SIZE);
-  mgos_cd_emit_footer();
+  mgos_cd_write();
 #endif
 #ifdef MGOS_HALT_ON_EXCEPTION
   mgos_cd_printf("Halting\n");

src/common/platforms/arm/arm_exc.h

+/*
+ * Copyright (c) 2014-2019 Cesanta Software Limited
+ * All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the ""License"");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an ""AS IS"" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+
+struct arm_exc_frame {
+  uint32_t r0;
+  uint32_t r1;
+  uint32_t r2;
+  uint32_t r3;
+  uint32_t r12;
+  uint32_t lr;
+  uint32_t pc;
+  uint32_t xpsr;
+#if __FPU_PRESENT
+  uint32_t s[16];
+  uint32_t fpscr;
+  uint32_t reserved;
+#endif
+} __attribute__((packed));
+
+struct arm_gdb_reg_file {
+  uint32_t r[13];
+  uint32_t sp;
+  uint32_t lr;
+  uint32_t pc;
+  uint32_t xpsr;
+#if __FPU_PRESENT
+  uint64_t d[16];
+  uint32_t fpscr;
+#endif
+  // MSP and PSP are our extension.
+  uint32_t msp;
+  uint32_t psp;
+} __attribute__((packed));
+
+void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
+                            struct arm_gdb_reg_file *rf);
+void arm_exc_dump_regs(void);

src/common/platforms/arm/arm_exc_top.S

@@ -30,10 +30,10 @@ arm_exc_handler_top:
   // r1 -> arm_exc_frame prepared for us by the CPU
 #if __FPU_PRESENT
   add r0, r1, #104  // sizeof(arm_exc_frame)
-  sub sp, #328      // sizeof(arm_gdb_reg_file)
+  sub sp, #208      // sizeof(arm_gdb_reg_file)
 #else
   add r0, r1, #32   // sizeof(arm_exc_frame)
-  sub sp, #328      // sizeof(arm_gdb_reg_file)
+  sub sp, #76       // sizeof(arm_gdb_reg_file)
 #endif
   mov r2, sp
   // r0 -> original sp, r2 -> arm_gdb_reg_file to fill
@@ -63,6 +63,17 @@ arm_exc_handler_top:
   str r3,  [r2, #60]
   ldr r3,  [r1, #28]  // xpsr
   str r3,  [r2, #64]
+#if __FPU_PRESENT
+  mrs r3,  msp
+  str r3,  [r2, #200] // msp
+  mrs r3,  psp
+  str r3,  [r2, #204] // psp
+#else
+  mrs r3,  msp
+  str r3,  [r2, #68] // msp
+  mrs r3,  psp
+  str r3,  [r2, #72] // psp
+#endif
 
   mrs r0, ipsr
   b arm_exc_handler_bottom