Skip to content

L
libyuv
Switch branch/tag
  1. 29 Aug, 2017 1 commit
  3. 25 Aug, 2017 1 commit
    • Frank Barchard's avatar
      Gaussian reorder for benefit of A73 · f0a9d6d2
      Frank Barchard authored 
      Roughly. instead of 4 loads and 8 multiples, use 1 load and 2 multiples
4 times over.  The original code, as with the C code from clang and gcc,
did all the loads, then all the math, then the store.  The new code
does a load, then the math, then the next load, etc.
This schedules better on current arm 64 cpus.
Number of registers also reduced, reusing the same registers.

HiSilicon ARM A73:

Now
TestGaussRow_Opt (890 ms)
TestGaussCol_Opt (571 ms)

Was
TestGaussRow_Opt (1061 ms)
TestGaussCol_Opt (595 ms)

Qualcomm 821 (Pixel):

Now
TestGaussRow_Opt (571 ms)
TestGaussCol_Opt (474 ms)

Was
TestGaussRow_Opt (751 ms)
TestGaussCol_Opt (520 ms)

TBR=kjellander@chromium.org
BUG=libyuv:719
TEST=LibYUVPlanarTest.TestGaussRow_Opt

Reviewed-on: https://chromium-review.googlesource.com/627478Reviewed-by: 's avatarCheng Wang <wangcheng@google.com>
Reviewed-by: 's avatarFrank Barchard <fbarchard@google.com>
Change-Id: I5ec81191d460801f0d4a89f0384f89925ff036de
Reviewed-on: https://chromium-review.googlesource.com/634448
Commit-Queue: Frank Barchard <fbarchard@google.com>
      f0a9d6d2
  5. 24 Aug, 2017 1 commit
  7. 22 Aug, 2017 1 commit
  9. 21 Aug, 2017 2 commits
  11. 18 Aug, 2017 1 commit
  13. 17 Aug, 2017 1 commit
  15. 16 Aug, 2017 1 commit
  17. 15 Aug, 2017 3 commits
  19. 14 Aug, 2017 2 commits
  21. 09 Aug, 2017 1 commit
  23. 04 Aug, 2017 1 commit
  25. 03 Aug, 2017 2 commits
  27. 02 Aug, 2017 1 commit
  29. 26 Jul, 2017 1 commit
  31. 25 Jul, 2017 2 commits
  33. 21 Jul, 2017 2 commits
  35. 20 Jul, 2017 2 commits
  37. 19 Jul, 2017 2 commits
  39. 13 Jul, 2017 1 commit
  41. 19 Jun, 2017 1 commit
  43. 13 Jun, 2017 1 commit
  45. 09 Jun, 2017 2 commits
  47. 07 Jun, 2017 3 commits
  49. 06 Jun, 2017 2 commits
  51. 01 Jun, 2017 1 commit
  53. 25 May, 2017 1 commit
    • Frank Barchard's avatar
      lint warning fixes for CpuID · 7bffe5e1
      Frank Barchard authored 
      The CpuId function is a wrapper for the intrinsic, or
implemented with inline if unavailable.  It had been
using uint32, but the intrinsics use int, so it was causing
casting and lint warnings.  This change makes the internal
implementation use int.

Casting was also done for xgetbv, and the cast is simply
removed, and is not causing a build error.

MipCpuCaps was doing strlen to check for white space after the
instruction set.  Arm also does this but with a hard coded offset.
This was causing a cast from size_t to int, which produced a lint
warning.  The change removes the white space detect.
In theory the code could be used to detect SSE vs SSE2, and it would
need to check SSE is followed by a space or end of line.  But this
code is only used on Arm and Mips, where there there is one form
of SIMD detected.  e.g. MSA for mips.  If a new instruction set is
added with a similar name, the write space check could be reintroduced.
But its more likely the code can be rewritten to use a better form
of detection by then. Or remove detection and require the instructions

BUG=libyuv:641
TEST=try bots build on all platforms without error and lint is clean

Change-Id: I9f55f8e57bba0f78571bdddbe63b945dea3e8809
Reviewed-on: https://chromium-review.googlesource.com/514524
Commit-Queue: Frank Barchard <fbarchard@google.com>
Reviewed-by: 's avatarCheng Wang <wangcheng@google.com>
Reviewed-by: 's avatarWan-Teh Chang <wtc@chromium.org>
      7bffe5e1